Commit ac42c210 authored by Jack Lange's avatar Jack Lange

enable covirt launch via launch flags

parent df462101
......@@ -98,7 +98,8 @@ pisces_launch(int pisces_id,
int cpu_id,
uintptr_t base_addr,
uintptr_t block_size,
int num_blocks)
int num_blocks,
uint32_t flags)
{
char * enclave_path = get_pisces_dev_path(pisces_id);
int ret = 0;
......@@ -111,6 +112,9 @@ pisces_launch(int pisces_id,
return -1;
}
boot_env.flags = flags;
/* Allocate N memory block from (optional) NUMA zone or as specified on cmd line*/
{
if (base_addr == PISCES_ANY_MEMBLOCK) {
......
......@@ -19,6 +19,10 @@
#define PISCES_ANY_NUMA_ZONE (-1)
/* Pisces Launch flags */
#define LAUNCH_VIRT_ENABLE 0x00000001
int pisces_load(char * kern, char * initrd, char * cmd_line);
int pisces_launch(int pisces_id,
......@@ -26,7 +30,8 @@ int pisces_launch(int pisces_id,
int cpu_id,
uintptr_t base_addr,
uintptr_t block_size,
int num_blocks);
int num_blocks,
uint32_t flags);
int pisces_get_cons_fd(int pisces_id);
......
......@@ -31,12 +31,12 @@ static void usage() {
int
main(int argc, char ** argv)
{
int numa_zone = PISCES_ANY_NUMA_ZONE;
int cpu_id = PISCES_ANY_CPU;
int base_addr = PISCES_ANY_MEMBLOCK;
int num_blocks = 1;
int enclave_id = -1;
int numa_zone = PISCES_ANY_NUMA_ZONE;
int cpu_id = PISCES_ANY_CPU;
int base_addr = PISCES_ANY_MEMBLOCK;
int num_blocks = 1;
int enclave_id = -1;
uint32_t flags = 0;
/* Parse options */
{
......@@ -48,6 +48,7 @@ main(int argc, char ** argv)
{"num-blocks", required_argument, 0, 'm'},
{"numa", required_argument, 0, 'n'},
{"cpu", required_argument, 0, 'c'},
{"virt", no_argument, 0, 'v'},
{0, 0, 0, 0}
};
......@@ -65,6 +66,9 @@ main(int argc, char ** argv)
case 'm':
num_blocks = atoi(optarg);
break;
case 'v':
flags |= LAUNCH_VIRT_ENABLE;
break;
case '?':
usage();
break;
......@@ -89,7 +93,7 @@ main(int argc, char ** argv)
}
}
if (pisces_launch(enclave_id, numa_zone, cpu_id, base_addr, pet_block_size(), num_blocks) != 0) {
if (pisces_launch(enclave_id, numa_zone, cpu_id, base_addr, pet_block_size(), num_blocks, flags) != 0) {
printf("Error: Could not launch enclave %d\n", enclave_id);
return -1;
}
......
......@@ -405,6 +405,7 @@ set_enclave_launch_args(struct pisces_enclave * enclave,
boot_params->launch_code_esi = esi;
boot_params->launch_code_target_addr = target_addr;
printk(KERN_DEBUG " set target address at %p to %p\n",
(void *) __pa(&(boot_params->launch_code_target_addr)),
(void *) boot_params->launch_code_target_addr);
......@@ -565,10 +566,16 @@ boot_enclave(struct pisces_enclave * enclave)
printk(KERN_DEBUG "Boot Enclave on CPU %d (APIC=%d)...\n",
enclave->boot_cpu, apicid);
set_enclave_launch_args(enclave,
boot_params->kernel_addr,
enclave->bootmem_addr_pa >> PAGE_SHIFT);
if (enclave->covirt_enabled == 0) {
set_enclave_launch_args(enclave,
boot_params->kernel_addr,
enclave->bootmem_addr_pa >> PAGE_SHIFT);
} else {
set_enclave_launch_args(enclave,
boot_params->covirt_addr,
enclave->bootmem_addr_pa >> PAGE_SHIFT);
}
if (pisces_setup_trampoline(enclave) != 0) {
......
......@@ -154,6 +154,7 @@ enclave_ioctl(struct file * filp,
enclave->bootmem_addr_pa = boot_env.base_addr;
enclave->bootmem_size = num_pages * PAGE_SIZE;
enclave->boot_cpu = boot_env.cpu_id;
enclave->covirt_enabled = !!(boot_env.flags & LAUNCH_VIRT_ENABLE);
pisces_enclave_add_cpu(enclave, boot_env.cpu_id);
......
......@@ -73,6 +73,9 @@ struct pisces_enclave {
struct list_head memdesc_list;
u32 memdesc_num;
int covirt_enabled;
};
......
......@@ -26,6 +26,7 @@
#include "enclave.h"
#include "boot.h"
#include "pisces_boot_params.h"
#include "covirt.h"
int pisces_major_num = 0;
struct class * pisces_class = NULL;
......@@ -147,8 +148,15 @@ device_ioctl(struct file * file,
}
case PISCES_LOAD_VMM: {
int fd = arg;
int fd = arg;
int ret = 0;
ret = covirt_load_vmm(fd);
if (ret == -1) {
printk(KERN_ERR "Could not load VMM\n");
return -EFAULT;
}
}
......
......@@ -21,6 +21,7 @@
#include "pisces_ringbuf.h"
#include "enclave_ctrl.h"
#include "pisces_xpmem.h"
#include "covirt.h"
#include "boot.h"
#include "pgtables.h"
......@@ -277,6 +278,30 @@ setup_boot_params(struct pisces_enclave * enclave)
}
/*
* Covirt launch code
*/
if (enclave->covirt_enabled) {
offset = ALIGN(offset, PAGE_SIZE_4KB);
boot_params->covirt_addr = __pa(base_addr + offset);
boot_params->covirt_size = covirt_get_vmm_size();
memcpy((void *)(boot_params->covirt_addr),
(void *)covirt_get_vmm_addr(),
boot_params->covirt_size);
offset += PAGE_SIZE_4KB;
printk("\tCovirt image loaded at %p (size=%llu)\n",
(void *)(boot_params->covirt_addr),
boot_params->covirt_size);
}
/*
* 1. kernel image
*/
......
......@@ -29,8 +29,9 @@ struct pisces_enclave;
* 2. Console ring buffer (64KB) // 4KB aligned
* 3. To enclave CMD buffer // (4KB)
* 4. From enclave CMD buffer // (4KB)
* 4. kernel image // bootmem + 2MB (MUST be loaded at the 2MB offset)
* 5. initrd // 2M aligned
* 5. Covirt Launch code // (4KB)
* 6. kernel image // bootmem + 2MB (MUST be loaded at the 2MB offset)
* 7. initrd // 2M aligned
*
*/
......@@ -79,6 +80,10 @@ struct pisces_boot_params {
// cmd_line
char cmd_line[1024];
// covirt launch code
u64 covirt_addr;
u64 covirt_size;
// kernel
u64 kernel_addr;
u64 kernel_size;
......
......@@ -29,11 +29,16 @@
#define PISCES_ENCLAVE_CTRL_CONNECT 2005
/* Pisces Launch flags */
#define LAUNCH_VIRT_ENABLE 0x00000001
struct enclave_boot_env {
unsigned long long base_addr;
unsigned long long block_size;
unsigned int num_blocks;
unsigned int cpu_id;
unsigned int flags;
} __attribute__((packed));
......
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